MRAM technology is a non-volatile random access memory technology that may replace present random access memories as the standard memory technology for computing devices. An MRAM cell (also referred to as a tunneling magnetoresistive or TMR-device) includes a structure having ferromagnetic layers respectively exhibiting a resultant magnetic moment vector separated by a non-magnetic layer (tunneling barrier) and arranged into a magnetic tunnel junction (MTJ). In contrast to non-volatile DRAM memory technology, digital information is not stored by power but rather is represented in the MRAM cell as directions of magnetic moment vectors (magnetization) in the ferromagnetic layers. More specifically, the magnetic moment vector of one ferromagnetic layer is magnetically fixed (or pinned), while the magnetic moment vector of the other ferromagnetic layer is free to be switched between the two preferred directions in the magnetization easy axis, which typically is arranged to be aligned with the fixed magnetization of the reference layer. In other words, a memory state of an MRAM cell is maintained by the direction of the magnetization of the free layer with respect to the direction of the magnetization of the reference layer.
Depending upon the two different magnetic states of the free layer, the MRAM cell exhibits two different resistance values in response to a voltage applied across the magnetic tunneling junction barrier. Accordingly, the particular resistance of the TMR-device reflects the magnetization state of the free layer, wherein the resistance is lower when the magnetization of the free layer is parallel to the magnetization of the reference layer, and higher when magnetizations are antiparallel. Hence, a detection of changes in resistance allows to provide information stored in the MRAM cell.
In order to switch MRAM cells, magnetic fields which are coupled to the freely switchable magnetization of the magnetic free layer are applied. The magnetic fields typically are generated by supplying currents to current lines, e.g., write bit and write word lines, crossing at right angles with an MRAM cell being positioned in an intermediate position therebetween and at an intersection thereof.
To be useful in electronic devices, MRAM cells must be arranged in high-density cell arrays. Accordingly, a further down-scale of individual MRAM cells, exhibiting a minimum feature size of about 65 nm or even less, is one of the most prominent aims to bring MRAM cells into practical use.
However, down-scaling MRAM cells to realize a minimum feature size being as small as 65 nm or below, causes severe problems as to the electromigration of the switching currents. In fact, it is expected that due to current density limitations because of the electromigration phenomenon, the switching currents will have to scale down to a level of about 0.5 mA.
Otherwise, down-scaling the MRAM cells requires smaller and smaller magnetic tunnel junctions, since for a given aspect ratio and given free layer thickness the magnetic switching fields increase roughly like
  1      w  or
      1    w    ,depending on the cell concept, where w is the width of the memory cell. More specifically, field selected switching becomes ever harder in case the width w of the memory is decreased requiring large switching currents.
Accordingly, down-scaling the MRAM cells requires large switching currents on the one hand which, however, are likely to induce electromigration phenomena on the other hand.
Until now, no solution as to the problem regarding prevention of electromigration of the switching currents in down-scaling MRAM cells has been offered. Future concepts as to high-dense MRAM cell arrays in the 65 nm minimum feature size technology and even below rather are based on the hope of still finding appropriate switching mechanisms which enable switching of the MRAM cells supplying smaller switching currents having a reduced tendency with respect to the undesired electromigration phenomenon which may even prevent the practical usage of high-dense MRAM cell arrays.
In light of the above, there is a need for methods of switching (writing) MRAM cells allowing a further cell size down-scale, in particular in realizing a 65 nm feature size technology or below, without thereby causing severe problems as to the undesired electromigration phenomenon.